gate delay meaning in Chinese
门信号延迟
门延迟
选通延迟
Examples
- Trigger gate delay
触发门脉冲延迟 - The problem in high speed signal process , such as parasitic parameter and gate delay is also the difficulty hi the research
生成高速，稳定的时钟信号是本课题的目标。高速信号处理所遇到的常见问题，如寄生参数，门电路延迟是设计难点。 - Due to the subtle error among different manufacturing equipment , the gate delay of circuits is different and varies in a given scope , which induces the time uncertainty of the waveform
由于制造设备本身存在微小误差，具体门的延时并不相同，而是在一定范围内变化，引起波形变化的时间不确定。 - This paper constructs a stable rlc interconnect model based on the first three moments of the node admittance , and discusses its application to interconnect delay and logic gate delay estimation
摘要基于rlc互连树节点导纳的低阶矩构建了一种稳定的互连模型，并讨论了它在互连树延时和逻辑门延时估计中的应用。 - When the silicon technology comes to deep sub - micron level , the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency , the allowable errors become smaller , and the influence of the transmission delay gets bigger , which increase the difficulty of the circuit design
在深亚微米制造技术中，芯片互连线延迟超过门延迟，而且随着集成电路工作频率的提高，允许的时序容差变小，传输延迟的影响加大，设计工作难度增加。